An image sensor is a semiconductor device that converts an optical image into an electrical signal.
As illustrated in example FIG. 1A, a method for fabricating a semiconductor device such as an LDI can include gates 54 for low voltage region 10, medium voltage region 20 and high voltage region 30 formed on and/or over semiconductor substrate 50 using photo mask 55. A thickness of gate insulating layer 52 at low voltage region 10 is less than that of gate insulating layer 52 at medium voltage region 20. The thickness of gate insulating layer 52 at medium voltage region 20 is less than that of gate insulating layer 52 in high voltage region 30. As illustrated in example FIG. 1B, after forming gates 54 at each region 10, 20, and 30, photo mask 55 is removed by an ashing and then stripping process. As illustrated in example FIG. 1C, photo masks 56 and 58 are formed to expose gate insulating layer 52 at high voltage region 30 while covering low voltage region 10 and medium voltage region 20. As illustrated in example FIG. 1D, the thickness of gate insulating layer 52 at high voltage region 30 is etched to the thickness of gate insulating layer 52 at medium voltage region 20 by a reactive ion etching using photo masks 56 and 58. As illustrated in example FIG. 1E, photo masks 56 and 58 are removed.
As illustrated in example FIGS. 1C and ID, with the method for fabricating the semiconductor device as described above, photo mask 56 may be formed on and/or over an uppermost surface of gate 54 at high voltage region 30. The reason is that when gate insulating layer 52 at high voltage region 30 is etched after exposing the entire gate 54 at high voltage region 30 without forming photo mask 56, the entire gate 54 is attacked upon etching gate insulating layer 52. Therefore, photo mask 56 is formed on and/or over gate 54 at high voltage region 30. If the width of photo mask 56 is largely formed to protect gate 54 at high voltage region 30, gate insulating layer 52 around gate 54 at high voltage region 30 cannot be etched. The width of photo mask 56 formed on the uppermost surface of gate 54 at high voltage region 30 may be formed less (for example, 100 nm or more) than that of gate 54 in process margins (overlay, CD variation). Exposed portions 62 and 64 of edges of gate 54 at high voltage region 30 are subjected to an etching poly attack upon etching gate insulating layer 52.